Formal connectivity verification has become an important part of the verification flow. Nonetheless, the sheer amount of connectivity information has grown to a point where elaboration of design description becomes cumbersome as the complexity of modern electronic designs grows.
Conventional approaches for connectivity verification often adopt brute force techniques that rely on the computing power of powerful computing systems to prove or disprove the connectivity of an electronic design. Some conventional approaches further perform full elaboration for an electronic design and/or perform connectivity verification on the entire set of connectivity. The ever increasing number of connections to be verified in a modern electronic design poses a serious challenge in the performance, speed, and efficiency to these conventional approaches.
Therefore, there exists a need for a method, system, and computer program product for connectivity verification in electronic designs.